1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
FIG. 1 is a layout view of part of a 3D vertical gate memory array with vertical gates at regular intervals. The layout view can be further understood in view of subsequent figures. Word lines 2, 4, and 6 run across the top surface of the 3D vertical gate memory array. Word line 2, 4, and 6 are electrically coupled to vertical gate columns (such as vertical gate columns 8, 10, 12, 14, and 16) running into the page. The vertical gate columns electrically that are coupled to the same word line are electrically isolated, by dielectric columns (such as dielectric columns 18, 20, 22, 24, and 26), from the vertical gate columns that are electrically coupled to an adjacent word line.
Conductive strips 28, 30, 32, and 34 are the top strip in a stack of strips that alternate between conductive and dielectric strips. Current flow through the conductive strips 28, 30, 32, and 34 is shown by respective arrows running the length of the conductive strips. In the direction running into the page, each stack of strips alternates between conductive and dielectric strips.
The vertical gate columns apply biases to control current flow in the conductive strips such as conductive strips 28, 30, 32, and 34. The vertical gate columns also control current flow in other conductive strips, not visible in the figure but positioned more deeply in the stacks of strips (more deeply in the direction running into the page).
Charge storage structures, such as charge storage structures 36, 38, 40, 42, 44, 46, 48, and 50, are positioned adjacent to both sides of the stacks of strips. An example of charge storage structures is silicon oxide-silicon nitride-silicon oxide. The charge stored in the proximate part of the charge storage structures alters the bias to be applied by the adjacent vertical gate column in order to cause current flow in the proximate part of the conductive strip.
Each memory device is a double gated device. The gates are on each side of the conductive strip acting as a channel. A charge storage structure is also on each side of the conductive strip acting as a channel, in between the conductive strip in the middle and each gate on each side of the conductive strip.
The vertical gate columns electrically coupled to a first word line are aligned with the vertical gate columns electrically coupled to a second word line adjacent to the first word line. Similarly, the dielectric columns on a first side of a particular word line are aligned with the dielectric columns on a second side of the particular word line; the first side and second side are on opposite sides of the particular word line. Word lines are positioned only over the vertical gate columns, and not positioned over the dielectric columns. The resulting large gaps between the word lines electrically coupled to aligned rows of vertical gate columns represent a design limit to memory density.
It would be desirable to increase the memory density of three-dimensional integrated circuit memory.